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Does not implement SWJ-DP
- SWD is often used as an acronym for both the SW-DP and SWJ-DP (Serial Wire JTAG Debug Port). The EFM32 does not implement SWJ-DP.
www.silabs.com/documents/public/application-notes/AN0043.pdf
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Does EFM32 implement SWJ-DP?
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Why does EFM32 use JTAG-to-SWD?
Does efm32/efr32/ezr32 have a Serial Wire Debug (SWD) interface?
The EFM32 does not implement SWJ-DP. All EFM32 devices also include the Serial Wire Output interface which is a one wire interface for the Instrumentation Trace Macrocell (ITM) which is a CoreSight module that provides coarse-grained time stamping and software driven trace information.
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The reason for the JTAG-to-SWD sequence is that the Debug Port implementation is actually a SWJ-DP. SWJ-DP is a wrapper around both SW-DP and JTAG-DP, the JTAG counterpart to SWD. The EFM32 does not include JTAG, but the switching sequence must still be performed as the default state required by the SWJ-DP specification is JTAG.
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The EFM32 does not implement SWJ-DP. All EFM32 devices also include the Serial Wire Output interface which is a one wire interface for the Instrumentation Trace Macrocell (ITM) which is a CoreSight module that provides coarse-grained time stamping and software driven trace information.
Jul 9, 2021 · Connecting to these pins allows an external device (such as a debug probe) to communicate directly with the Serial Wire Debug Port (SW-DP). The SW-DP can then access one or several Access Ports (APs) that give access to the rest of the system.
- 1. Introduction
- 2. Serial Wire Debug overview
- 3. SWD protocol
- 4. Serial Write Debug Port(SW-DP) Registers
- 5. Memory Access Port(MEM-AP) Registers
- 6. Debug and system Registers
- 7. SRAM programing
- 8. Source code
- 9. Reference
- LICENSE
This documentation describe how to programming ARM Cortex M3 internal SRAM over SWD(Serial Wire Debug) interface. For this purpose, something we too know.
•SWD communication protocol. We need to know Low level timing requirement, that is foundation to exchange command and data between debugger and target MCU.
•Read/write data from/to internal SRAM. We need to know how to program firmware into desired address, like SRAM(0x20000000). That needs us to know SW-DAP registers usage. Pass address and data over those registers and then into internal SRAM.
•Make code running from SRAM. We need to change vector table entry from internal flash to SRAM; And SP and PC also needed change to SRAM location. That need us to know the cortex M3 debug and system registers usage.
Serial Wire Debug (SWD) is a 2-pin (SWDIO/SWCLK) electrical alternative JTAG interface that has the same JTAG protocol on top. SWD uses an ARM CPU standard bi-directional wire protocol, defined in the ARM Debug Interface v5. This enables the debugger to become another AMBA bus master for access to system memory and peripheral or debug registers.
The Debug Access Port(DAP) is split into two main control units. the Debug Port (DP) and the Access Port (AP), and the physical connection to the debugger is part of the DP. The DAP supports two types of access, Debug Port (DP) accesses and Access Port (AP)accesses. External device to communicate directly with Serial Wire Debug Port(SW-DP) over SWDIO/SCLK pins. And SW-DP in turn can access one or several Access Ports(APs) the give access to the rest of the system. The MEM-AP is important AP which provide a way to access all memory and peripheral registers residing on the internal AHB/APB buses.
Figure 1 ARM Debug Interface MEM-AP Implementation
One of the four registers within the DP is the AP Select Register, SELECT. This register specifies a particular Access Port, and a bank of four 32-bit words within the register map of that AP. It enables up to 256 Access Ports to be implemented, and gives access to any one of 16 four-word banks of registers on the selected AP.
3.1. Connection and line reset sequence
The SW-DP must use connection sequence of 50 clock cycles with data = 1. And this sequence is also used as a line reset sequence which requires 50 consecutive 1s on the data input. JTAG to SWD switching SWJ-DP enables either an SWD or JTAG protocol to be used on the debug port. To do this, it implements a watcher circuit that detects a specific 16-bit selection sequence on the SWDIOTMSpin: The 16-bit JTAG-to-SWD select sequence is defined to be 0b0111100111100111, MSB first. This can be represented as 16'h79E7 if transmitted MSB first or 16'hE79E if transmitted LSB first. The host must read IDCODE register after line request sequence. This requirement gives confirmation that correct packet frame alignment has been achieved.
3.2. Successful transaction operation
A successful transaction contains three phases. •Host sending an eight-bit write packet request to target. •Target response with a three-bit OK acknowledge to host. •A 33-bit data phase, either from host or target depends on write/read operation. Figure 2 Serial Wire Debug successful write operation
3.2.1. Packet request phase
The request phase consists of 8 bits. The meaning of each bit in the request is illustrated below. •Start -- A single start bit, with value 1. •APnDP -- A single bit, indicating whether the Debug Port or the Access Port Access Register is to be accessed. 1 for accessing AP. •RnW -- A single bit, this bit is 0 for an write access, or 1 for a read access. •A[2:3] -- Two bits, giving the A[3:2] address field for the DP or AP register address. •Parity -- A single even parity bit is made over the APnDP, RnW and A[2:3] bits. The number of bits set to 1 is odd, then the parity bit is set to 1. •Stop -- A single stop bit. In the synchronousSWD protocol this is always 0. •Park -- A single bit, with value 1.
4.1. The Identification Code Register, IDCODE
IDCODE register provides a identification information about SW-DP. On the EFM32 or SiM3U devices with a Cortex-M3 or Cortex-M4 core this register should read 0x2BA01477. For devices with a CortexM0+ core the register should read 0x0BC11477.
4.2. The AP Abort Register, ABORT
ABORT register main purpose is to force a DAP abort, and on a SW-DP it is also used to clear error and sticky flag conditions. Here are the bit assignments of AP Abort register. Table 2 ABORT register bit assignments You might want to find what caused the flag to be set to 1. Typically: •For the STICKYCMP or STICKYERR flag, you must find which location was accessed to cause the flag to be set to 1. •For the WDATAERR flag, you must resend the corrupted data. •For the STICKYORUN flag, you must find which DP or AP transaction caused the overflow. You then have to repeat your transactions from that point.
4.3. The Control/Status Register, CTRL/STAT
CTRL/STAT register provides control of the DP and status information about the DP. Figure 3 Control/Status Register bit assignments •Bit [28] CDBGPWRUPREQ is the signal from the debug interface to the power controller, used to request the system power controller to fully power-up and enable clocks in the debug power domain. •Bit [30] CSYSPWRUPREQ is the signal from the debug interface to the power controller, used to request the system power controller to fully power-up and enable clocks in the system power domain. The debugger must write a 1 to the CDBGPWRUPREQ and CSYSPWRUPREQ bits before using the AHB-AP. The STICKYERR bit is set if an error is returned by a AP transaction. While the STICKYERR bit is set any SWD request will return a FAULT response. To clear the STICKYERR bit, use the ABORT register.
5.1. Control/Status Word (CSW) Register
CSW register configures and controls accesses through the MEM-AP to or from a connect memory system. Table 5 Bit assignments for the MEM-AP Control/Status Word Register, CSW
5.2. The Transfer Address Register (TAR)
TAR register holds the memory address to be accessed. The contents of TAR can be incremented automatically on a successful DRW access with b01 set in AddrInc field of CSW register.
5.3. The Data Read/Write Register (DRW)
DRW register is used to either write or read from the address held in TAR. To write a value to an internal memory address, first write the address to the TAR register, then write the value to DRW. To read a memory address, first write the address to TAR, then read the value in DRW.
6.1. Debug Halting Control and Status Register, DHCSR
DHCSR register controls halting debug. Halting debug is enabled when C_DEBUGEN is set to 1. Table 7 DHCSR bit assignments
6.2. Debug Core Register Selector Register, DCRSR
DCRSR register provides debug access to the ARM core registers, special-purpose registers, and Floating-point extension registers. A write to DCRSR specifies the resister to transfer. Table 8 DCRSR bit assignments DebugReturnAddress is the address of the first instruction to be executed on exit from Debug state.
6.3. Debug Core Register Data Register, DCRDR
DCRDR register provides debug access to ARM core register, special-purpose registers,and Floating-point extension registers. The DCRDR is the data register for these accesses. Use of DCRSR and DCRDR •To transfer a data word to an ARM core register, special-purpose register, orFloating-point extension register, a debugger: •Writes the required word to DCRDR. •Writes to the DCRSR, with the REGSEL value indicating the required register, and the REGWnR bit as 1 to indicate a write access. This write clears the DHCSR S_REGRDY bit to 0. •If required, polls DHCSR until DHCSR.S_REGRDY reads-as-one. This shows that the processor has transferred the DCRDR value to the selected register. •To transfer a data word from an ARM core register, special-purpose register, or Floating-point extension register, a debugger: •Writes to the DCRSR, with the REGSEL value indicating the required register, and the REGWnR bit as 0 to indicate a read access. This write clears the DHCSR.S_REGRDY bit to 0. •Polls DHCSR until DHCSR.S_REGRDY reads-as-one. This shows that the processor has transferred the value of the selected register to DCRDR. •Reads the required value from DCRDR.
7.1. Initialization
Before suing the SW-DP an initialization sequence must be performed to establish communication and bring the SW-DP to a know state. •Send more than 50 SWCLKTCK cycles with SWDIOTMS=1. This ensures that both SWD and JTAG are in their reset states. •Send the 16-bit JTAG-to-SWD select sequence on SWDIOTMS •Send more than 50 SWCLKTCK cycles with SWDIOTMS=1. This ensures that if SWJ-DP was already in SWD mode, before sending the select sequence, the SWD goes to line reset. •Perform a READID to validate that SWJ-DP has switched to SWD operation.
7.2. Halt the core
Before programming internal SRAM, the ARM Cortex M3 should first be reset and halted. It gets the core and peripherals into a know state and prohibit the core from accidentally running partial code while writing the program. There debug and system registers and one Silabs extent AP register CHIPAP_CTRL1 are used for this purpose. CHIPAP_CTRL1 address = 0x1, APSEL = 0x0A. bit 3 core_reset_ap, To hold the CortexM3 core in reset this bit should be written to one. The process is as follow: •Write 0x08 to CHIPAP_CTRL1. •Write 0xA05F0001 to DHCSR, which halting debug enabled. •Write 0x01 to DEMCR. This enable Reset Vector Catch. •Write 0xFA050004 to AIRCR. This reset the core. •Write 0x00 to CHIPAP_CTRL1. Now the core will be halted on first instruction and all peripherals and registers will have their reset value.
7.3.1 Access memory
•Set 32 bit width and auto increment in CSW register. •Write memory address in TAR register •Access DRW register for read/write data. Here is the python script example
Source code can be found at https://github.com/MarkDing/swd_programing_sram
•Adi5 ARM Debug Interface v5 Architecture Specification.
•Adi51 ARM Debug Interface v5 Architecture Specification ADIv5.1 Supplement.
•Cm3trm Cortex-M3 Revision r2p1 Technical Reference Manual
•ARMv7-M ARMv7-M Architecture Reference Manual
The MIT License (MIT)
Copyright (c) 2014 Mark Ding(mark.ding@hotmail.com)
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sub-license, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
1.1.1 EFM32 STK The EFM32GG_STK3700 and EFM32WG_STK3800 can be used as the EFM32 STK hardware platform of the standalone program-mer. • Handy, plug and run: no host PC is required. • On board SEGGER JLink debugger and USB virtual COM port (CDC). • Supports USB host, and MCU can run up to 48 MHz.
EFM32 Debug and Trace - AN0043 - Application Note - Energy Micro
