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Oct 20, 2021 · Viewed 5k times. 2. I have seen the abbreviation PHY beeing used for a handful of different things within the context of Ethernet: a PHY is a type of Ethernet physical layer (eg. 100BASE-TX, 10BASE-T) a PHY is an Ethernet transceiver IC (eg. an IC that converts 100BASE-TX to MII/RMII) a PHY is a physical layer device (more than just the ...
A PHY chip or layer converts data between a "clean" clocked digital form which is only suitable for very-short-distance (i.e. inches) communication, and an analogue form which is suitable for longer range transmission. It has no particular clue as to what any of the bits "mean", nor how they should be interpreted or assembled.
What you really need is a different variety of PHY, so called "backplane phy". Those are specifically designed to work with capacitive coupling over PCB traces. The relevant standard is called 802.3ap. Here's a nice overview: Many modern PHYs can be put into a 1000Base-KX mode through a bit of configuration tweaking.
Dec 16, 2022 · The PHY also dissipates a significant amount of power all by itself. And sometimes different media require different PHYs, but the MAC can be the same. For all of these reasons, it makes sense to keep it as a separate chip. That said, there are some chips targeted for embedded applications that include both.
Aug 10, 2023 · Using the existing UTMI+ specification as a starting point, the ULPI working group reduced the number of interface signals to 12 pins, with an optional implementation of 8 pins. The package size of PHY and Link IC’s are drastically reduced. This not only lowers the cost of Link and PHY IC’s, but also makes for a smaller PCB.
Feb 9, 2023 · The "PHY address" you refer to is an MDIO bus address. MDIO is a management interface between a MAC and one or more PHYs. In the case of the W5500, the MAC and PHY are integrated in the chip. Refer to the W5500 block diagram (green lines added by me): So there's no need for an external management interface, or for PHYAD pins.
Sep 1, 2010 · 12. I'm trying to connect an RJ-45 jack with integrated magnetics (Belfuse L829-1X1T-91 datasheet) to an Ethernet PHY chip (Micrel KSZ8041TL datasheet). The TX+/-, RX+/-, and the LED pins are all easy enough to figure out, but I'm not sure what to do with the center taps (TCT and RCT) for the transformers. Should they be connected to 3.3 V power?
Jan 10, 2013 · It looks like you have isolated the PHY's power nicely with L10 and bypass caps C69-C74. All you need to do is connect all the PHY grounds together, then make sure that net has exactly one connection to the main ground. That keeps the nasty high frequency loop currents local, but still gives the PHY the same 0V reference as the rest of the board.
Jul 11, 2018 · This specific datasheet doesn't specify what the value for the RSET resistor should be. But after a bit of looking around, I found another for a Realtek IC (PHY) which uses a bandgap reference as well and they use a value of 2.49k for that resistor. The regulator voltages are about the same for both ICs (1.05V vs 1.0V).
Sep 27, 2022 · The TX pins on the 100Mbps PHY should connect to the RX pins on the gigabit PHY (which are on the B pair). If you are wiring an RJ45 straight-through (not crossover) cable, then the TX pair would be on A+/A- (pins 1 and 2), and the RX pair would be on B+/B- (pins 3 and 6).
