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Apr 12, 2024 · Bruno Lévy's homepage. Computational Physicist, Inria Research Director (DR0) ParMA project-team. U. Paris-Saclay, Inria Saclay, CNRS, Labo. de Maths d'Orsay. Scientific Director of the Inria Quadrant program. Member of Inria Evaluation Committee. Bruno.Levy@inria.fr. Latest news. 08/11-16/2024: BIRS Workshop Optimal Transport and Dynamics (Oaxaca)
- Bruno Levy's home page - GitHub Pages
Bruno Levy's homepage, Inria researcher on geometry...
- Bruno Levy's home page - GitHub Pages
Researcher in computational physics, Scientific director of Inria Quadrant Program, 2018-2022 director of centre Inria Nancy Grand-Est, ERC GOODSHAPE. 596 followers · 5 following.
- Saclay, France
- @INRIA
Bruno Levy's home page. Monge-Ampère gravitation. Monge-Ampère gravity, 60 Mpc/h, 256^3 particles. Monge-Ampère gravity, 300 Mpc/h, 512^3 particles. Fluid simulation videos. Crown splash.
- Overview
- FemtoRV: a minimalistic RISC-V CPU
- Playing with LiteX: plug-and-play system to assemble SOCs
- From Blinky to RISC-V
- Basic: more basic things I wrote during May 2020 - June 2020
Learning FPGA, yosys, nextpnr, and RISC-V
Mission statement: create teaching material for FPGAs, processor design and RISC-V, using around $40 per students.
FemtoRV is a minimalistic RISC-V design, with easy-to-read Verilog sources directly written from the RISC-V specification. The most elementary version (quark), an RV32I core, weights 400 lines of VERILOG (documented version), and 100 lines if you remove the comments. There are also more elaborate versions, the biggest one (petitbateau) is an RV32IM...
The repository includes LiteX examples. The LiteX framework is a well designed and an easy-to-use framework to create SoCs. It lets you create a SoC by assembling components (processor, SDRAM controller, SDCard controller, USB, ...) in Python. FemtoRV is directly supported by LiteX (that directly downloads it from this repository when selected as t...
In Episode I, you will learn to build your own RISC-V processor, step by step, starting from the simplest design (that blinks a LED), to a fully functional RISC-V core that can compute and display graphics.
In Episode II, you will learn how to design a pipelined processor.
Files are here. This includes:
•Blinker: the "hello world" program
•LedMatrix: play with a 8x8 let matrix, driven by a MAX7219 IC.
•OLed: play with a SSD1351 OLed display, driven by a 4-wire SPI protocol.
•Serial: access the included USB-virtual UART pins
•LedTerminal: display scrolling messages on the LED matrix, obtained from the USB virtual UART
Bruno Lévy (born 3 August 1979) is a French artist living in New York City. His artwork deals primarily with creating dynamic relationships between audio and video.
Bruno Lévy. Inria Nancy Grand-Est, LORIA, France, Stéphane P.A. Bordas. Faculté des Sciences, de la Technologie et de la Communication, University of Luxembourg, Luxembourg. School of Engineering, Cardiff University, CF24 3AA Wales, UK. Institute of Research and Development, Duy Tan University, K7/25 Quang Trung, Danang, Viet Nam
